With the recent advancements in integrated circuit (IC) technology, ICs are becoming increasingly complex on one hand and more compact on the other. With the reduction in size of transistors on the ICs, a level of power supply supplied to the ICs is also reducing. As a result, the IC standards have shifted focus from 5 Volts (V) power supply to lower voltages, such as 3.3 V and 1.8 V. The low voltages of power supply offer various advantages, namely, lower power consumption and reduced capacitance in between lines.
However, new system components, based on the new standards of lower power supply, should be backward compatible with the existing system components operating on 5V power supply. For this, various schemes offer mixed voltage integrated circuits, in which a circuit operating at a low voltage can communicate with a circuit operating at a high voltage. For example, input and output (IO) buffers are implemented to facilitate communication between the components working on different voltage standards.
The IO buffers include level shifters and drivers, which interface with different components having different operating voltages. Generally, the level shifters and drivers use thick oxide transistors, which can tolerate up to 5V. However, the usage of thick oxide transistors is associated with two main problems. First, the thick oxide transistors cover substantial PCB real estate and second, more number of processing steps are needed to fabricate an IO buffer.
Also, while the level shifter and driver stages have thick oxide transistors, other stages of the IO buffer may be fabricated from thin oxide transistors. Using different kinds of transistors further increases the number of processing steps and hence, adds to the overall cost of the IC.
Thus, certain schemes have been devised to implement the complete circuitry with the thin oxide transistors alone. However, the thin oxide transistors may not be able to support high voltage overdrives. Thus, some schemes either suggest the use of parallel architectures or a level shifter, which has transistors in cascode circuit arrangements to limit voltage stress on the driver. In such circuit arrangements, a problem arises if a cascode transistor is faulty because a switching transistor will be subjected to whatever voltage stress the cascode device was designed to limit, thus damaging the switching transistor and the IC permanently. Such structural failures may be detrimental to the system in which the IC is implemented.
In addition, such a cascode circuit arrangement of thin oxide transistors operates on the basis of an externally generated reference, which is distributed on the reference rails to the I/O buffer chain, which limits the speed of operation of the integrated circuit to 5 MHz as transistor is stressed between any two terminals during the transients. The problem of stress on the switching transistors increases at increasing speeds. Some schemes have suggested the use of a triple cascode circuit arrangement to reduce the level of stress. However, implementations of such schemes occupy a significant amount of extra silicon area.